Josiah Mendes

Release Notes

Last Updated: 2023-07-01

Aug 2022 - May 2023 Year Abroad at the National University of Singapore, building RISCALAR under the supervision of Dr. Rajesh Panicker.

Apr 2022 - Aug 2022 Industry placement at Arm in CPU Performance Team working on microarchitecture modelling and CI/CD automation.

Jun 2021 - Aug 2021 Summer internship at Arm doing UVM verification, creating a register model to track read and writes.

Feb 2021 - Undefined Started as a CPU Part Time Undegraduate at Arm Ltd.

Sep 2019 - Jun 2023 Began an Masters in Electronic and Information Engineering with Year Abroad at Imperial College London.

Jun 2019 Graduated from YCIS Qingdao, China with IB & IGCSE certifications.


Skills

  • Familiar with SystemVerilog / Verilog, Rust, Python, C++, Dart
  • Knowledgable in Computer Architecture and μArch, Automation Scripting and Flutter framework and packages
  • Bilingual in English and Chinese (Mandarin)

CV in PDF format