Here is a selection of projects that I have worked on both in university and in my spare time. Have a look at the links in the descriptions for more information.
RISCALAR
A cycle-approximate, parametrisable RISC-V μArch educational simulator designed to allow students to understand trade-offs between perf, power and area. See the IEEE ISCAS 2024 Preprint for more. Built with Rust for fast performance and development speed and Flutter for cross-platform compatibility.
Function Accelerator
A study in SW/HW co-design to accelerate the computation of a function that involved multiplication, division, summation and trigometry on a Terasic DE1-SoC board, moving from a soft core software solution to taking advantage of the reconfigurable logic.
MIPS32-T501
Lead architect for the team designing a low power, high performance 32-bit, 5-stage partially MIPS-compliant core. Designed with future implementation of pipelining in mind and optimised for frequency performance through systematic critical path analysis.
FPGA Computer Vision for Object Detection
Led hardware ISP vision pipeline Verilog development for an autonomous Mars Rover. Used CV techniques such as colour space transforms to draw bounding boxes and calculate object distances for mapping with SystemVerilog, DE10-Lite and Quartus.
ImFresh
An IoT device utilising air quality data and humidity sensors to remind people of the right time to do your laundry. Designed app using Flutter to communicate with the Raspberry Pi over MQTT.
Issie
Contributed to this cross-platform hardware design application written in F# together with the Elmish framework. Adding functionality for customisable symbols and better interfaces for diagram drawing and simulation.
Synthesiser
Firmware for realtime operation including multi-tone, multi-keys and CAN communication. Built with C++ on a a ST NUCLEO-L432KC microcontroller
Intelligently Built Microprocessors
A custom 16-bit Instruction Set and Processor using Quartus Prime & Verilog optimised for efficient recursion, random number generation and linked list traversing. Focused on stack design and clock frequency optimisation through tooling.